1. Field of the Invention
The present invention relates generally to data transceivers.
2. Background Art
A communication device including a transmitter and a receiver is known as a transceiver. Known transceivers can transmit and receive data signals. There are demands on such transceivers to transmit and receive such data signals with low error rates and at ever increasing data rates, to reduce power dissipation, cost, and size. Therefore, there is a general need for a transceiver capable of satisfying such demands.
It is desirable to integrate transceiver circuits on an integrated circuit (IC) chip to reduce size and power dissipation of the transceiver. The circuits on the IC chip typically operate in accordance with timing signals. However, oscillators used to generate such timing signals have disadvantages, including typically large sizes, high power dissipation, and deleterious electromagnetic radiative properties (that is, the oscillators tend to radiate electromagnetic interference across the IC chip). Also, oscillators used in communication devices often need to be tunable in both phase and frequency and in response to rapidly changing signals. This requires complex oscillator circuitry. Moreover, multiple oscillators on a common IC chip are subjected to undesired phenomena, such as phase and/or frequency injection locking, whereby one oscillator can deleteriously influence the operation of another oscillator.
Therefore, there is a general need to integrate transceiver circuits on an IC chip. There is a related need to reduce the number and complexity of oscillators constructed on the IC chip, to thereby avoid or substantially reduce all of the above-mentioned disadvantages associated with such oscillators.
To reliably process a received data signal, a receiver typically needs to match its operating characteristics with the characteristics of the received data signal. For example, in the case of baseband data transmissions, the receiver can derive a sampling signal, and then use the sampling signal to sample the received data signal at sample times that produce optimal data recovery. In this way, data recovery errors can be minimized.
Precision timing control techniques are required to achieve and maintain such optimal sampling times, especially when the received data signals have high data rates, such as multi-gigabit-per-second data rates. Such timing control includes control of the phase and frequency of a sampling signal used to sample the received data signal.
As the received data signal rate increases into the multi-gigabit-per-second range, the difficulty in effectively controlling sampling processes in the receiver (such as controlling phase and frequency characteristics of the sampling signal) correspondingly increases. For example, semiconductor circuits, such as complementary metal oxide semiconductor (CMOS) circuits, are often unable to operate at sufficiently high frequencies to optimally control the sampling processes. For example, it becomes increasingly difficult at such high received signal data rates to provide sufficiently short time delays usable for controlling sampling phases of the sampling signal.
Accordingly, there is a need for systems and techniques in a data receiver that provide effective sampling of high data rate signals. There is a related need to reduce the number of circuit components required to provide such effective data signal sampling, thereby reducing cost, size, and power dissipation in the data receiver.
I. Phase Interpolator
The present invention is directed to a phase interpolation system. The phase interpolation system includes a stage controller adapted to produce a plurality of stage control signals, and a plurality of reference stages that are each adapted to convert one of a plurality of reference signals into a corresponding component signal. Each reference stage performs this conversion in response to a respective one of the stage control signals. Each of the component signals has a distinct phase that is determined by the corresponding reference signal phase.
The phase interpolation system also includes a combining node that is adapted to combine (e.g., sum) the component signals into an output signal having an interpolated phase.
Each of the plurality of reference stages may include a conversion module and one or more scaling modules. The conversion module is adapted to convert the corresponding reference signal into the corresponding component signal according to a scaling factor. The one or more scaling modules are adapted to adjust the scaling factor in response to a value of the corresponding stage control signal.
Each of the stage control signals may include a plurality of binary control subsignals. In this embodiment, the value of each stage control signal is the sum of the corresponding binary control signals. Each of these subsignals may be received by one of a plurality of scaling modules. As a result, the scaling factor of the respective reference stage increases with the value of the corresponding stage control signal.
In a specific implementation, four reference stages are each adapted to convert one of four reference signals into a corresponding component signal in response to a respective one of the stage control signals. These four reference signals each have one of four phases that are separated at substantially 90 degrees intervals.
The conversion module of each reference stage may include a transconductance device, such as a field effect transistor (FET).
The output signal as well as each of the reference and component signals may be differential signals.
The stage controller may be a phase control signal rotator adapted to adjust the plurality stage control signals such that the output signal is phase aligned with a serial data signal.
Without the use of conventional techniques, such as time-delays, the phase interpolator advantageously provides output signal phases that span a complete rotation of 360 degrees.
II. Timing Recovery System
A receiver of the present invention includes a timing recovery system to recover timing information from a received serial data signal. The receiver uses such recovered timing information to compensate for frequency and phase offsets that can occur between the received serial data signal and a receiver sampling signal used to sample the serial data signal. The timing recovery module of the present invention recovers/extracts phase and frequency information from the received serial data signal. The timing recovery module derives the sampling signal using the phase and frequency information. The timing recovery module phase aligns and frequency synchronizes the sampling signal with the serial data signal to enable the receiver to optimally sample the serial data signal.
The timing recovery system of the present invention includes a phase interpolator. The phase interpolator derives a sampling signal having an interpolated phase in response to 1) phase control inputs derived by the timing recovery system, and 2) a set of reference signals derived from a master timing signal. The timing recovery system causes the interpolator to align the interpolated phase of the sampling signal with the serial data signal phase. In addition, the timing recovery system can cause the interpolator to rotate the interpolated phase of the sampling signal at a controlled rate to synchronize the sampling signal frequency to the serial data signal frequency.
The present invention advantageously simplifies a master oscillator used to generate the master timing signal (mentioned above) because the phase interpolator, not the oscillator, tunes the phase and frequency of the sampling signal. In other words, the master oscillator need not include complex phase and frequency tuning circuitry, since the need for such functionality is met using the timing recovery system. Additionally, multiple, independent timing recovery systems can operate off of a single, common master timing signal, and thus, a single master oscillator. This advantageously reduces to one the number of master oscillators required in a multiple receiver (that is, channel) environment on an IC chip. In such a multiple receiver environment, each of the multiple independent timing recovery systems (and interpolators) can be associated with each one of the multiple receivers. Each timing recovery system can track the phase and frequency of an associated one of multiple receive data signals, thus obviating the need for more than one oscillator.
In one embodiment, the present invention is directed to a system for recovering timing information from a serial data signal. The system comprises a phase interpolator adapted to produce a timing signal having an interpolated phase responsive to a plurality of phase control signals. The system further comprises a phase controller adapted to derive a rotator control signal based on a phase offset between the received data signal and the timing signal. The system further comprises a phase control signal rotator adapted to rotate the plurality of phase control signals and correspondingly the interpolated phase of the timing signal in response to the rotator control signal. The phase controller is adapted to cause the phase control signal rotator to rotate the plurality of phase control signals and correspondingly the interpolated phase of the timing signal in a direction to reduce the phase offset between the received data signal and the timing signal. The rotator control signal is one of a phase-advance, a phase-retard, and a phase-hold signal. The phase control signal rotator rotates the plurality of phase controls signals in a first direction to advance the interpolated phase of the timing signal in response to the phase-advance signal, rotates the plurality of phase controls signals in a second direction to retard the interpolated phase in response to the phase-retard signal, and prevents the plurality of phase control signals and correspondingly the interpolated phase from rotating in response to the phase-hold signal.
In another embodiment, the present invention is directed to a method of recovering timing information from a serial data signal. The method comprises deriving a timing signal having an interpolated phase in response to a plurality of phase control signals, deriving a rotator control signal based on a phase offset between the received data signal and the timing signal, and rotating the plurality of phase control signals and correspondingly the interpolated phase of the timing signal in response to the rotator control signal.
In still another embodiment, the present invention is directed to a system for recovering timing information from a serial data signal. The system comprises a phase interpolator adapted to derive a sampling signal having an interpolated phase based on a plurality of control signals. The system further comprises a controller coupled to the phase interpolator. The controller includes a phase error processor adapted to derive an estimate of a frequency offset between the sampling signal and the serial data signal. The controller causes the phase interpolator to rotate the interpolated phase of the sampling signal at a rate corresponding to the frequency offset so as to reduce the frequency offset between the sampling signal and the serial data signal.
In yet another embodiment, the present invention is directed to a method of recovering timing information from a serial data signal. The method comprises deriving a sampling signal having an interpolated phase, estimating a frequency offset between the sampling signal and the serial data signal, and rotating the interpolated phase of the sampling signal at a rate corresponding to the frequency offset, thereby reducing the frequency offset between the sampling signal and the serial data signal. The method also comprises repetitively rotating the interpolated phase of the sampling signal through a range of phases spanning 360xc2x0 at the rate corresponding to the frequency offset. The method also comprises rotating the interpolated phase of the sampling signal in a direction of increasing phase to decrease a frequency of the sampling signal when the frequency of the sampling signal is greater than a frequency of the serial data signal, and rotating the interpolated phase of the sampling signal in a direction of decreasing phase to increase a frequency of the sampling signal when the frequency of the sampling signal is less than the frequency of the serial data signal.
III. High-Speed Serial Data Transceiver
The present invention provides a multiple-receiver transceiver (also referred to as a multi-channel transceiver), on an IC chip. This is also referred to herein as a multi-channel communication device, on an IC chip. The communication device advantageously includes only a single master timing generator (that is, oscillator module), to reduce power consumption, size, part count and complexity, and avoid problems associated with multiple oscillator architectures, such as those described above. Each receiver in the communication device can process (that is, recover data from) a respective received, analog serial data signal having a multi-gigabit-per-second data rate. Each receiver is associated with an independently operating timing recovery system, including a phase interpolator, for phase and frequency tracking the respective received, analog serial data signal.
In an embodiment, the present invention is directed to a communication device on an IC chip. The communication device comprises a master signal generator adapted to generate a master timing signal, and a receive-lane adapted to receive an analog serial data signal. The receive-lane includes a sampling signal generator adapted to generate multiple time-staggered sampling signals based on the master timing signal, and multiple data paths each adapted to sample the serial data signal in accordance with a corresponding one of the time-staggered sampling signals. The multiple data paths thereby produce multiple time-staggered data sample streams. The communication device also includes a data demultiplexer module adapted to time-deskew and demultiplex the multiple time-staggered data streams. The serial data signal has a multi-gigabit symbol rate. Each of the time-staggered sampling signals, and correspondingly, each of the time-staggered data sample streams, has a data rate below the multi-gigabit symbol rate. The data demultiplexer is adapted to produce a demultiplexed data sample stream representative of the serial data signal having the multi-gigabit symbol rate.
In another embodiment, the present invention is directed to a method in a communication device. The method comprises generating a master timing signal, and generating multiple time-staggered sampling signals based on the master timing signal. The method further comprises sampling a received, analog serial data signal in accordance with each of the multiple time-staggered sampling signals, thereby producing multiple time-staggered data sample streams. The method further comprises time-deskewing the multiple time-staggered data streams to produce multiple time-deskewed data streams, and demultiplexing the multiple time-deskewed data streams.
In yet another embodiment, the present invention is directed to a communication device on an IC chip. The device is configured to receive multiple, analog serial data signals. The device comprises a master timing generator adapted to generate a master timing signal. The device also includes multiple receive-lanes, each configured to receive an associated one of the multiple serial data signals. Each receive-lane includes a phase interpolator adapted to produce a sampling signal having an interpolated phase, and a data path adapted to sample and quantize the associated serial data signal in accordance with the sampling signal. The device also includes an interpolator control module coupled to each receive-lane. The interpolator control module is adapted to cause the phase interpolator in each receive-lane to rotate the interpolated phase of the sampling signal in the receive-lane at a rate corresponding to a frequency offset between the sampling signal and the serial data signal associated with the receive-lane, so as to reduce the frequency offset between the sampling signal and the serial data signal.
In an even further embodiment, the present invention is directed to a method in a communication device configured to receive multiple serial data signals. The method comprises generating a master timing signal, and deriving multiple sampling signals based on the master timing signal. Each of the multiple sampling signals is associated with one of the multiple serial data signals and each of the sampling signals has an interpolated phase. The method further comprises sampling and quantizing each of the multiple serial data signals according to the associated one of the sampling signals. The method also comprises rotating the interpolated phase of each sampling signal at a rate corresponding to a frequency offset between the sampling signal and the serial data signal associated with the receive-lane so as to reduce the frequency offset between the sampling signal and the serial data signal. The method also comprises rotating each interpolated sampling signal phase independently of the other one or more interpolated sampling signal phases.
The sampling signal (mentioned above) and the serial data signal are considered xe2x80x9cphase-alignedxe2x80x9d when their respective phases are such that the sampling signal causes the serial data signal to be sampled at or acceptably near an optimum sampling time for sampling the serial data signal.
xe2x80x9cFrequency synchronizedxe2x80x9d or xe2x80x9cfrequency matchedxe2x80x9d means the frequencies of the sampling signal and serial data signal are related to one another such that the sampling signal and the serial data signal do not tend to xe2x80x9cdriftxe2x80x9d in time relative to one another. For example, once initially phase-aligned, the sampling signal and the serial data signal will remain phase-aligned over time as long as the sampling signal and the serial data signal are frequency synchronized. An exemplary frequency matching condition corresponds to when the frequency of the serial data signal is an integer multiple (that is, one, two, etc.) of the frequency of the sampling signal.
When the sampling signal and the serial data signal are xe2x80x9cfrequency offsetxe2x80x9d from one another, the two signals are not frequency synchronized. xe2x80x9cNullingxe2x80x9d such a frequency offset causes the sampling and serial data signals to be frequency synchronized.
The above defined terms xe2x80x9cphase-aligned,xe2x80x9d xe2x80x9cfrequency synchronized,xe2x80x9d xe2x80x9cfrequency matched,xe2x80x9d xe2x80x9cfrequency offset,xe2x80x9d and xe2x80x9cnullingxe2x80x9d shall be construed to be consistent with their usage in the following description.